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[AMD] Tune Kimi-K2.5 MXFP4 MI355X vLLM toward ATOM parity / 调优 Kimi-K2.5 MXFP4 MI355X vLLM,缩小与 ATOM 的性能差距#2213

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[AMD] Tune Kimi-K2.5 MXFP4 MI355X vLLM toward ATOM parity / 调优 Kimi-K2.5 MXFP4 MI355X vLLM,缩小与 ATOM 的性能差距#2213
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@Fangzhou-Ai Fangzhou-Ai commented Jul 14, 2026

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Summary

  • Apply the accuracy-gated candidate settings for amd/Kimi-K2.5-MXFP4 on MI355X with vLLM TP4.
  • Keep image: TBD intentionally. This draft must not receive a sweep label until an official upstream vLLM ROCm image includes the required AITER MXFP4 backend.
  • Preserve the existing TP4 and TP8 search spaces and extend only conc-end from 64 to 128 for both fixed-sequence workloads. Local evidence covers TP4 1k/1k at concurrency 4, 16, 32, and 128; TP8, the remaining points, and 8k/1k remain pending the official-image sweep.
  • This changes benchmark configuration only; it does not patch vLLM or AITER source code.
  • This draft replaces closed [Superseded] Kimi-K2.5 MI355X tuning draft / [已替代] Kimi-K2.5 MI355X 调优草稿 #2212 after cleaning internal experiment labels from the branch and PR metadata.

Effective settings

VLLM_ROCM_USE_AITER=1
VLLM_ROCM_QUICK_REDUCE_QUANTIZATION=INT4
VLLM_ROCM_USE_AITER_FUSION_SHARED_EXPERTS=1
VLLM_ROCM_USE_SKINNY_GEMM=0
VLLM_ROCM_USE_AITER_RMSNORM=0  # TP4
AITER_MXFP4_INTERMEDIATE=1
AITER_BYPASS_TUNE_CONFIG=0
AITER_MOE_SORT_BACKEND=auto
OMP_NUM_THREADS=1

--kv-cache-dtype fp8
--block-size 16
--max-num-batched-tokens 16384
--max-num-seqs 512
--async-scheduling
--no-enable-prefix-caching

The recipe also preserves the existing 0.90 GPU-memory utilization, MEC firmware workaround, trusted remote code, and multimodal encoder TP mode. It enforces a minimum server context of 9472 tokens so the 1k/1k configuration matches the locally validated server.

Local validation

These results validate local vLLM 94c0ef300 with AITER b2dd7703d, not the pending image:

1k/1k TP4 concurrency Candidate total tok/s/GPU ATOM total tok/s/GPU Candidate / ATOM
4 227.71 246.47 92.39%
16 591.09 640.77 92.25%
32 843.05 918.26 91.81%
128 1736.45 1833.73 94.69%
  • GSM8K: 1319/1319 requests, 97.35% strict and flexible exact match.
  • bash -n benchmarks/single_node/fixed_seq_len/kimik2.5_fp4_mi355x.sh
  • Targeted matrix generation: 24 configurations, TP {4,8} × concurrency {4,8,16,32,64,128} × {1k/1k,8k/1k}.

AITER requirement

The tested kernel path requires:

  1. ROCm/aiter e7731930 / #3753: transitional FlyDSL 0.2.1 bump.
  2. ROCm/aiter 26d40611 / #3764: FlyDSL 0.2.2 compatibility and pin.
  3. ROCm/aiter b2dd7703d / #3832: gfx950 RadeonFlow MXFP4 MoE backend and Kimi tuning.

Pinning b2dd7703d or a released descendant is sufficient because it already contains the first two commits. AITER v0.1.17-rc0 contains FlyDSL 0.2.2 but predates #3832, so it cannot reproduce the tested GEMM1/GEMM2 path.

Relationship to #2203

This is a materially different, measured alternative to #2203; only one should merge. #2203 copies K2.6-derived settings such as block size 1, 65,536 batched tokens, AITER RMSNorm, and custom MLA/compilation choices. This draft carries the locally validated Kimi-K2.5 settings that passed throughput scaling and full GSM8K evaluation.

Draft blockers

  • Publish and insert an official upstream vLLM ROCm image containing AITER #3832 or a validated successor.
  • Finish/update the matching upstream vllm-project/recipes documentation required by InferenceX policy.
  • Run full-sweep-fail-fast, including evals, on the final image.
  • Coordinate final disposition with Update kimik2.5 fp4 mi355x vLLM config #2203.

AI assistance was used to prepare the benchmark configuration and PR text. The submitter must review and defend every changed line.

中文说明

  • 为 MI355X 上的 amd/Kimi-K2.5-MXFP4 vLLM TP4 基准测试应用已通过精度验证的候选配置。
  • 有意保留 image: TBD。在上游正式发布包含所需 AITER MXFP4 后端的 vLLM ROCm 镜像之前,本草稿 PR 不应添加扫描标签。
  • 保留现有 TP4 和 TP8 搜索空间,仅将两个固定序列长度负载的 conc-end 从 64 扩展到 128。本地数据覆盖 TP4 1k/1k 的并发点 4、16、32 和 128;TP8、其余并发点与 8k/1k 需要在正式镜像发布后通过 CI 扫描验证。
  • 本 PR 只修改基准测试配置,不修改 vLLM 或 AITER 源码。
  • 本草稿用于替代已关闭的 [Superseded] Kimi-K2.5 MI355X tuning draft / [已替代] Kimi-K2.5 MI355X 调优草稿 #2212,并清理了分支及 PR 元数据中的内部实验标签。

“Effective settings”代码块列出了完整启动配置。该配置还保留现有的 0.90 GPU 显存利用率、MEC 固件规避措施、trust-remote-code 和多模态编码器 TP 模式,并将服务端最小上下文长度设为 9472,以对齐本地验证的 1k/1k 配置。

本地验证

上表数据来自本地 vLLM 94c0ef300 与 AITER b2dd7703d,不代表待发布镜像的结果:候选配置在并发 4、16、32、128 下达到 ATOM 吞吐量的 91.81%–94.69%。GSM8K 共完成 1319/1319 个请求,严格和宽松 exact match 均为 97.35%。Shell 语法检查通过;定向矩阵生成了 24 个配置,即 TP {4,8} × 并发 {4,8,16,32,64,128} × {1k/1k,8k/1k}

AITER 依赖

所测内核路径需要 ROCm/aiter e7731930(#3753,过渡到 FlyDSL 0.2.1)、26d40611(#3764,兼容并固定 FlyDSL 0.2.2)以及 b2dd7703d(#3832,为 gfx950 增加 RadeonFlow MXFP4 MoE 后端和 Kimi 调优)。直接使用 b2dd7703d 或包含它的后续正式版本即可,因为该提交已经包含前两项。

AITER v0.1.17-rc0 虽然包含 FlyDSL 0.2.2,但发布时间早于 #3832,因此无法复现本次验证所用的 GEMM1/GEMM2 路径。

#2203 的关系

本 PR 是与 #2203 实质不同、具有实测依据的替代方案,两者最终只能合并一个。#2203 复用了 K2.6 配置,包括 block size 1、65,536 batched tokens、AITER RMSNorm 以及自定义 MLA/编译选项;本草稿采用已完成吞吐量扩展测试和完整 GSM8K 评估的 Kimi-K2.5 候选配置。

草稿阻塞项

  • 发布并填入包含 AITER #3832 或已验证后续版本的上游正式 vLLM ROCm 镜像。
  • 按 InferenceX 要求完成或更新对应的上游 vllm-project/recipes 文档。
  • 使用最终镜像运行包含精度评估的 full-sweep-fail-fast
  • Update kimik2.5 fp4 mi355x vLLM config #2203 协调最终处理方式。

本 PR 的基准配置和说明文本使用了 AI 辅助。提交者必须逐行审核,并能够完整解释和维护这些改动。

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Thanks for the contribution! Please reach out to respective companies' CODEOWNER to fill in the latest PR_REVIEW_CHECKLIST.md before pinging core maintainer on Slack for review. In order for the signoff PR check bot to trigger, you must follow the PR_REVIEW_CHECKLIST.md template correctly, including the phrase As a PR reviewer and CODEOWNER, I have reviewed this and have.

For PR verification, add the full-sweep-fail-fast label (strongly recommended) to this PR — the benchmark sweep only runs on labeled PRs. Use full-sweep-enabled only if you need matrix jobs to keep running past a failure.

PR authors are responsible for ensuring that after merging, all GitHub Action jobs fully pass. A lot of the time, failures are just flakes and simply re-running the failed jobs will fix it. See GitHub's docs on re-running failed jobs


感谢你的贡献!请联系相应公司的 CODEOWNER 填写最新的 PR_REVIEW_CHECKLIST.md,然后再在 Slack 上联系核心维护者进行审阅。为了触发 signoff PR 检查机器人,你必须正确遵循 PR_REVIEW_CHECKLIST.md 模板,包括保留英文语句 As a PR reviewer and CODEOWNER, I have reviewed this and have

如需进行 PR 验证,请为此 PR 添加 full-sweep-fail-fast 标签(强烈推荐)— 基准测试 sweep 仅在带有标签的 PR 上运行。仅当需要矩阵任务在失败后继续运行时才使用 full-sweep-enabled

PR 作者有责任确保合并后所有 GitHub Action 任务完全通过。 很多时候失败只是偶发抖动(flake),重新运行失败的任务即可解决。参见 GitHub 关于重新运行失败任务的文档

Comment thread configs/amd-master.yaml Outdated
Apply the accuracy-gated serving settings, preserve the existing TP4 and TP8 matrix dimensions, extend only their concurrency upper bounds to 128, and keep the image as a draft placeholder pending the required AITER bump.

中文:应用已通过精度验证的服务配置,保留现有 TP4 和 TP8 矩阵维度,仅将并发上限扩展到 128,并暂时保留镜像占位符,等待所需的 AITER 版本升级。
@Fangzhou-Ai
Fangzhou-Ai force-pushed the perf/kimi-k2.5-mi355x-tp4 branch from 9ba5d2b to 1d24294 Compare July 14, 2026 22:51
Fangzhou-Ai and others added 3 commits July 14, 2026 18:55
… vLLM

Replace image: TBD with rocm/vllm-dev:nightly_cdna4, the latest gfx950 serving
image. It ships AITER 0.1.19.dev (>= v0.1.16.post5 from vllm-project/vllm#48683)
including the ROCm/aiter#3832 gfx950 MXFP4 MoE backend required by this recipe.

中文:将 image: TBD 替换为最新的 gfx950 服务镜像 rocm/vllm-dev:nightly_cdna4。
该镜像内置 AITER 0.1.19.dev(不低于 vllm-project/vllm#48683 引入的 v0.1.16.post5),
包含本配方所需的 ROCm/aiter#3832 gfx950 MXFP4 MoE 后端。

Co-authored-by: Cursor <cursoragent@cursor.com>
@Fangzhou-Ai
Fangzhou-Ai marked this pull request as ready for review July 21, 2026 17:46
@Fangzhou-Ai
Fangzhou-Ai requested a review from a team July 21, 2026 17:46
Fangzhou-Ai and others added 3 commits July 21, 2026 17:49
…-tp4

Co-authored-by: Cursor <cursoragent@cursor.com>

# Conflicts:
#	configs/amd-master.yaml
#	perf-changelog.yaml
…MI355X vLLM

Use the reproducible dated build tag
rocm/vllm-dev:nightly_cdna4_main_torch_2.11.0_rocm7.14.0a20260623_0721_b101
(same digest as floating nightly_cdna4) instead of the moving nightly_cdna4 tag.

中文:改用可复现的带日期构建标签
rocm/vllm-dev:nightly_cdna4_main_torch_2.11.0_rocm7.14.0a20260623_0721_b101
(与浮动的 nightly_cdna4 同一 digest),替换会被覆盖的 nightly_cdna4 标签。

Co-authored-by: Cursor <cursoragent@cursor.com>
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TP4/TP8 runs OOM during CUDA-graph capture: MI355X nodes hold ~30 GiB
per GPU outside the vLLM process, so a 0.90 budget (259 GiB) leaves 0
bytes physically free and capture buffers cannot allocate. 0.85 keeps
weights + KV inside 288 - 30 GiB with headroom for graph capture.

中文:将 MI355X 的 gpu-memory-utilization 从 0.90 下调到 0.85。TP4/TP8
在 CUDA graph 捕获阶段发生显存溢出——MI355X 节点每张卡有约 30 GiB 被
vLLM 进程之外占用,0.90 的预算(259 GiB)导致物理显存无剩余,捕获缓冲无法
分配。0.85 使权重与 KV 缓存控制在 288 - 30 GiB 内,为 graph 捕获留出余量。

Co-authored-by: Cursor <cursoragent@cursor.com>
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vllm-project/recipes#660

Comment thread configs/amd-master.yaml Outdated
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Fangzhou-Ai and others added 3 commits July 22, 2026 19:36
The AITER MXFP4 MoE bump (vllm-project/vllm#48683 / ROCm/aiter#3832) has
landed in the floating rocm/vllm-dev:nightly_cdna4 tag, so drop the
immutable dated pin and track nightly_cdna4 directly.

中文:改为跟踪浮动的 rocm/vllm-dev:nightly_cdna4 标签。AITER MXFP4 MoE
的版本提升(vllm-project/vllm#48683 / ROCm/aiter#3832)已合入 nightly_cdna4
浮动标签,因此去掉固定日期的镜像 pin,直接跟踪 nightly_cdna4。

Co-authored-by: Cursor <cursoragent@cursor.com>
…MI355X

Switch the kimik2.5-fp4-mi355x-vllm image from the rocm/vllm-dev CDNA4
nightly to the official vllm/vllm-openai-rocm nightly, commit-pinned to
the immutable nightly-387189c42997b27e2c04b5d97ef8190ffa2bf909 tag
(latest as of 2026-07-22). It carries the AITER MXFP4 MoE bump
(vllm-project/vllm#48683 / ROCm/aiter#3832) while staying reproducible.

中文:将 kimik2.5-fp4-mi355x-vllm 的镜像从 rocm/vllm-dev CDNA4 nightly
切换为官方 vllm/vllm-openai-rocm nightly,并按提交固定到不可变的
nightly-387189c42997b27e2c04b5d97ef8190ffa2bf909 标签(截至 2026-07-22
最新)。该镜像已包含 AITER MXFP4 MoE 的版本提升
(vllm-project/vllm#48683 / ROCm/aiter#3832),同时保持可复现。

Co-authored-by: Cursor <cursoragent@cursor.com>
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As a PR reviewer and CODEOWNER, I have reviewed this and have:

  • Verified that as of the moment of typing this, this is the latest version of PR_REVIEW_CHECKLIST.md
  • Verified that the general code quality meets the InferenceX standard and does not make the code quality any worse.
  • Verified that this PR has passed PR validation. Please link to GitHub Action workflow that shows this. Link: https://github.com/SemiAnalysisAI/InferenceX/actions/runs/29953041481
  • Verified that this PR passes evals. Please link to GitHub Action workflow that shows this. Range: 96.89%-97.42%, link: https://github.com/SemiAnalysisAI/InferenceX/actions/runs/29953041481
  • Verified that speculative decoding PRs uses chat templates to align the AL distribution to real world
  • For agentic workloads: verified that speculative-decoding configs (EAGLE / MTP / draft models) run with simulated synthetic acceptance, with the acceptance-length value taken from the committed golden AL curve in golden_al_distribution/ for that model, thinking mode, and draft length. A submission may choose any supported draft length, but it may not substitute a different acceptance target.
  • Verified that the model architecture isn't changed with benchmark hacks like using --hf-overrides to skipping indexer for every x layers on models that don't natively support this. As a general rule, we won't accept optimizations that reduces the number of model architecture FLOPs. Anything that makes that same computation run faster is fair game; FLOPs at lower precisions is fine, given that the config passes private evals. As an general north star princple, we should only use optimizations which is used in production by customers that care about accuracy
  • If an company claims that they support vLLM/SGLang as first class LLM inference engines on their hardware, I have verified that the respective vLLM submission made using upstream https://hub.docker.com/u/vllm docker repo, upstream SGLang https://hub.docker.com/u/lmsysorg docker repo. The only exceptions are for new hardware, such as MI455X UALoE72, Vera Rubin NVL72, Rubin NVL8, etc., and for new model architectures where there is an actual reason why vLLM/SGLang does not fundamentally support them yet as supported by vLLM/SGLang community maintainers
  • If an company claims that they support vLLM/SGLang as first class upstream in-tree LLM inference engines on their hardware, I have have verified that the respective vLLM/SGLang submission has been made before additional frameworks (TRT-LLM, ATOM, etc.). The only exceptions are for new hardware, such as MI455X UALoE72, Vera Rubin NVL72, Rubin NVL8, etc., and for new model architectures where there is an actual reason why vLLM/SGLang does not fundamentally support them yet.
  • Verified that every single-node vLLM/SGLang recipe in this PR is documented in the official vLLM recipes and/or the SGLang cookbook:
    • I linked the corresponding upstream PR in the vLLM recipe repo or SGLang repo and verified that it is MERGED before this InferenceX PR merges. An opened, draft, or closed-without-merge upstream PR does not satisfy this requirement. If the matching recipe was already published, I linked the published recipe/cookbook page in the additional detail section below.
  • Verified that this PR does not patch the inference engine or serving stack — the pinned image must run as shipped. This covers .patch files / git apply / patch, inline patches embedded in benchmark scripts (e.g. a python3/sed heredoc that rewrites installed engine sources before serving), in-place edits of site-packages, monkey-patching, overwriting container files, and installing forked/rebuilt engine wheels on top of the pinned image. The only exception is a patch covered by a filled-out waiver at docs/waiver/<PR_NUMBER>.md — named after the PR that introduces the patch and filed in that same PR, stating what is patched, why the unmodified upstream image cannot run this benchmark, the upstream PR/issue link, and the removal plan — which I have linked below in the additional detail section.
  • If any of the above criteria cannot reasonably be satisfied, I have provided additional reasoning below.

Additional detail section:

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/reuse-sweep-run

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❌❌❌ REJECTED ❌❌❌

@chunfangamd — blocking: the linked recipe documents a different model. This PR benchmarks amd/Kimi-K2.5-MXFP4, but vllm-project/recipes#660 documents amd/MiniMax-M3-MXFP4. No merged/published upstream recipe reproduces the Kimi-K2.5 MI355X recipe, so Check 3 fails.

➖ Check 0 (CODEOWNER): PASS — @chunfangamd owns configs/amd-master.yaml; the script + perf-changelog.yaml are catch-all (* @InferenceX/core) covered by any CODEOWNER.
✅ Check 1 (green in-PR sweep+eval): PASS — head 45c6584 has executed, green single-node 8k1k / and eval / jobs in run 29953041481 (1k1k skip is expected — the config sweeps only 8k1k).
✅ Check 2 (eval accuracy): PASS — GSM8K em_strict 96.89%–97.42% (n=1319) on amd/Kimi-K2.5-MXFP4, same image vllm/vllm-openai-rocm:nightly-387189c... as this PR's config.
❌ Check 3 (recipe merged+complete): FAIL — recipe #660 is MERGED but documents amd/MiniMax-M3-MXFP4, not this PR's amd/Kimi-K2.5-MXFP4; model/model-path is a MAJOR arg and does not match (recipe is MiniMax-specific: --tool-call-parser minimax_m3, --reasoning-parser minimax_m3). Link the merged Kimi-K2.5 recipe. (The PR's own draft blocker "Finish/update the matching upstream recipes documentation" is unchecked.)
✅ Check 4 (reuse command): PASS — /reuse-sweep-run posted by @chunfangamd (COLLABORATOR).
✅ Check 5 (latest template): PASS — all current-template items present; unchecked items (agentic spec-decode, catch-all reasoning) are non-applicable conditionals.
✅ Check 6 (upstream image / engine-first): PASS — vllm/vllm-openai-rocm:nightly-387189c... is upstream vLLM org; framework vllm on established SKU MI355X. Engine-first N/A (vLLM entry).
✅ Check 7 (no arch hacks): PASS — no --hf-overrides; fp8 KV-cache, block-size, batched-tokens are serving config, not FLOPs reduction.
➖ Check 8 (spec-decode chat template): N/A — no speculative-decoding changes.
✅ Check 9 (no engine patch): PASS — env-var exports and serve args only; no patch/heredoc/wheel rewrite of the engine.
➖ Check 10 (agentic golden AL): N/A — no agentic speculative-decoding changes.

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vllm-project/recipes#673

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@claude check the recipe RP: vllm-project/recipes#673

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Klaud-Cold commented Jul 23, 2026

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Claude finished @chunfangamd's task in 1m 19s —— View job


Recipe PR check — vllm-project/recipes#673

✅ This resolves the Check 3 blocker

Recipe #673"[ROCm] Document Kimi-K2.5 MXFP4 MI355X benchmark reproduction" — is MERGED (merged 2026-07-23T08:19:11Z by @xianbaoqian, merge commit 0885682), and unlike the previously-linked #660 it documents the correct model.

Item Status
Merged into main ✅ MERGED
File touched models/moonshotai/Kimi-K2.5.yaml (+56/−4)
Model / model-path amd/Kimi-K2.5-MXFP4 — matches this PR
Hardware / lane ✅ MI355X, TP4 high-concurrency benchmark lane

This is the fix for the earlier Klaud-Cold rejection, which failed Check 3 solely because #660 documented amd/MiniMax-M3-MXFP4. #673 adds a dedicated "MXFP4 benchmark reproduction (InferenceX MI355X sweep)" section to the Kimi-K2.5 recipe.

Settings cross-check (recipe vs. this PR's config)

The recipe's reproduction section matches this PR's effective settings:

  • Env vars all present and equal: VLLM_ROCM_USE_AITER=1, VLLM_ROCM_QUICK_REDUCE_QUANTIZATION=INT4, VLLM_ROCM_USE_AITER_FUSION_SHARED_EXPERTS=1, VLLM_ROCM_USE_SKINNY_GEMM=0, VLLM_ROCM_USE_AITER_RMSNORM=0, AITER_MXFP4_INTERMEDIATE=1, AITER_BYPASS_TUNE_CONFIG=0, AITER_MOE_SORT_BACKEND=auto, OMP_NUM_THREADS=1. ✅
  • Serve args match: --tensor-parallel-size 4, --kv-cache-dtype fp8, --block-size 16, --max-num-batched-tokens 16384, --max-num-seqs 512, --async-scheduling, --no-enable-prefix-caching, --mm-encoder-tp-mode data. ✅
  • MAX_MODEL_LEN >= 9472 guard documented, matching the 1k/1k validated server. ✅
  • Uses upstream vllm/vllm-openai-rocm:nightly. ✅

One minor discrepancy (non-blocking)

The merged recipe reproduction command shows --gpu-memory-utilization 0.85, whereas this PR's body and config state 0.90. This is not a Check-3 concern (model/model-path is the MAJOR arg and matches), but for exact reproduction fidelity you may want to align the recipe's gpu-memory-utilization with the benchmarked 0.90, or note why the sweep uses 0.90 while the recipe documents 0.85.

Bottom line: #673 satisfies the merged-upstream-recipe requirement for amd/Kimi-K2.5-MXFP4 that #660 did not. The draft blocker "Finish/update the matching upstream recipes documentation" can now be checked, and a re-run of the Klaud-Cold gate should clear Check 3. Worth updating the linked recipe in the PR checklist from #660#673.
· branch perf/kimi-k2.5-mi355x-tp4

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@claude I approve this PR because the reported issue has been resolved.

Signed: @chunfangamd

@Klaud-Cold

Klaud-Cold commented Jul 23, 2026

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Claude finished @chunfangamd's task in 1m 42s —— View job


Approval acknowledged — one step still needed to flip the red check

Thanks @chunfangamd. I've verified the resolution, and the underlying blocker is resolved — but the codeowner-signoff-verify status check is still red, and a comment approval alone won't turn it green. Here's the exact state.

What's resolved ✅

  • Recipe (Check 3): vllm-project/recipes#673 is MERGED (merge commit 0885682, by @xianbaoqian) and documents the correct modelmodels/moonshotai/Kimi-K2.5.yaml for amd/Kimi-K2.5-MXFP4. This is the fix for the earlier Klaud-Cold rejection, which failed only because Enable fast mode for Claude Code workflows #660 documented amd/MiniMax-M3-MXFP4.
  • Official image: configs/amd-master.yaml now pins the upstream vllm/vllm-openai-rocm:nightly-387189c… build (no more image: TBD), satisfying the engine-first / upstream-image requirement.
  • Settings ↔ recipe match: the script's effective settings (--kv-cache-dtype fp8, --block-size 16, --max-num-batched-tokens 16384, --max-num-seqs 512, --async-scheduling, --gpu-memory-utilization 0.85, the AITER env vars, and the MAX_MODEL_LEN >= 9472 guard) line up with the merged recipe. Note the earlier "0.90 vs 0.85 discrepancy" is now gone — commit 19100b1 lowered util to 0.85, matching [AMD] Add ATOM+MTP, dsr1 fp8/fp4 #673.

What still blocks the green check ⚠️

The commit status codeowner-signoff-verify on head 45c6584 is failure, pointing at the Klaud-Cold rejection from 2026-07-23 05:40 — that verdict was computed before #673 merged (08:19), and against your APPROVED checklist whose Additional detail section still links the wrong recipe:

### Additional detail section:
https://github.com/vllm-project/recipes/pull/660   ← MiniMax-M3, stale

To clear the gate:

  1. Update the sign-off checklist so the Additional detail section links [AMD] Add ATOM+MTP, dsr1 fp8/fp4 #673 instead of Enable fast mode for Claude Code workflows #660, and check the draft blocker "Finish/update the matching upstream recipes documentation." Fix this →
  2. Re-run the sign-off verification (e.g. re-post /reuse-sweep-run or re-trigger the Klaud-Cold gate) so it re-evaluates against the now-merged [AMD] Add ATOM+MTP, dsr1 fp8/fp4 #673. Check 3 should then pass, and with Checks 0–2 and 4–9 already green the status should flip to success.

One note on the PR body

The PR description still reads image: TBD and cites --block-size 16 … 0.90 / 1k/1k local validation, but the branch has since pinned the official nightly, lowered util to 0.85, and (per perf-changelog.yaml) deprecated 1k1k in favor of the 8k1k sweep (#2263). Worth refreshing the body so it matches the merged config — cosmetic, not a merge blocker.

I can't approve the PR myself (that's disabled for the bot for security reasons), but once the checklist link is corrected and the sign-off gate re-runs, this should be green and mergeable.
· branch perf/kimi-k2.5-mi355x-tp4

@chunfangamd

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As a PR reviewer and CODEOWNER, I have reviewed this and have:

  • Verified that as of the moment of typing this, this is the latest version of PR_REVIEW_CHECKLIST.md
  • Verified that the general code quality meets the InferenceX standard and does not make the code quality any worse.
  • Verified that this PR has passed PR validation. Please link to GitHub Action workflow that shows this. Link: https://github.com/SemiAnalysisAI/InferenceX/actions/runs/29953041481
  • Verified that this PR passes evals. Please link to GitHub Action workflow that shows this. Range: 96.89%-97.42%, link: https://github.com/SemiAnalysisAI/InferenceX/actions/runs/29953041481
  • Verified that speculative decoding PRs uses chat templates to align the AL distribution to real world
  • For agentic workloads: verified that speculative-decoding configs (EAGLE / MTP / draft models) run with simulated synthetic acceptance, with the acceptance-length value taken from the committed golden AL curve in golden_al_distribution/ for that model, thinking mode, and draft length. A submission may choose any supported draft length, but it may not substitute a different acceptance target.
  • Verified that the model architecture isn't changed with benchmark hacks like using --hf-overrides to skipping indexer for every x layers on models that don't natively support this. As a general rule, we won't accept optimizations that reduces the number of model architecture FLOPs. Anything that makes that same computation run faster is fair game; FLOPs at lower precisions is fine, given that the config passes private evals. As an general north star princple, we should only use optimizations which is used in production by customers that care about accuracy
  • If an company claims that they support vLLM/SGLang as first class LLM inference engines on their hardware, I have verified that the respective vLLM submission made using upstream https://hub.docker.com/u/vllm docker repo, upstream SGLang https://hub.docker.com/u/lmsysorg docker repo. The only exceptions are for new hardware, such as MI455X UALoE72, Vera Rubin NVL72, Rubin NVL8, etc., and for new model architectures where there is an actual reason why vLLM/SGLang does not fundamentally support them yet as supported by vLLM/SGLang community maintainers
  • If an company claims that they support vLLM/SGLang as first class upstream in-tree LLM inference engines on their hardware, I have have verified that the respective vLLM/SGLang submission has been made before additional frameworks (TRT-LLM, ATOM, etc.). The only exceptions are for new hardware, such as MI455X UALoE72, Vera Rubin NVL72, Rubin NVL8, etc., and for new model architectures where there is an actual reason why vLLM/SGLang does not fundamentally support them yet.
  • Verified that every single-node vLLM/SGLang recipe in this PR is documented in the official vLLM recipes and/or the SGLang cookbook:
    • I linked the corresponding upstream PR in the vLLM recipe repo or SGLang repo and verified that it is MERGED before this InferenceX PR merges. An opened, draft, or closed-without-merge upstream PR does not satisfy this requirement. If the matching recipe was already published, I linked the published recipe/cookbook page in the additional detail section below.
  • Verified that this PR does not patch the inference engine or serving stack — the pinned image must run as shipped. This covers .patch files / git apply / patch, inline patches embedded in benchmark scripts (e.g. a python3/sed heredoc that rewrites installed engine sources before serving), in-place edits of site-packages, monkey-patching, overwriting container files, and installing forked/rebuilt engine wheels on top of the pinned image. The only exception is a patch covered by a filled-out waiver at docs/waiver/<PR_NUMBER>.md — named after the PR that introduces the patch and filed in that same PR, stating what is patched, why the unmodified upstream image cannot run this benchmark, the upstream PR/issue link, and the removal plan — which I have linked below in the additional detail section.
  • If any of the above criteria cannot reasonably be satisfied, I have provided additional reasoning below.

Additional detail section:

@Klaud-Cold

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✅✅✅ Verdict: PASS ✅✅✅

Supersedes the earlier REJECTED verdict on this SHA: that gate ran before vllm-project/recipes#673 merged and against the stale #660 link. The current sign-off links #673 (now MERGED), which documents the correct model, so Check 3 now passes. Green run: 29953041481.

✅ Check 0 (CODEOWNER): PASS — @chunfangamd owns configs/amd-master.yaml; the script + perf-changelog.yaml are catch-all (* @InferenceX/core), covered by any CODEOWNER.
✅ Check 1 (green in-PR sweep+eval): PASS — head 45c6584 has executed, green single-node 8k1k / (TP4/TP8) and per-config eval / jobs in run 29953041481 (1k1k skip is expected — config sweeps 8k1k only).
✅ Check 2 (eval accuracy): PASS — GSM8K em_strict 96.89%–97.42% (n=1319) on amd/Kimi-K2.5-MXFP4, same image vllm/vllm-openai-rocm:nightly-387189c… as this PR's config.
✅ Check 3 (recipe merged+complete): PASS — recipes#673 is MERGED (2026-07-23) and documents amd/Kimi-K2.5-MXFP4 (MI355X TP4 sweep). Major args match: model, TP4, kv-cache-dtype fp8, block-size 16, batched-tokens 16384, max-num-seqs 512, async-scheduling, gpu-mem-util 0.85, and the AITER MXFP4 env vars.
✅ Check 4 (reuse command): PASS — /reuse-sweep-run posted by @chunfangamd (COLLABORATOR).
✅ Check 5 (latest template): PASS — all current-template items present; the two unchecked items (agentic spec-decode, catch-all reasoning) are non-applicable conditionals.
✅ Check 6 (upstream image / engine-first): PASS — vllm/vllm-openai-rocm:nightly-387189c… is the upstream vLLM org; framework vllm on established SKU MI355X. Engine-first N/A (vLLM entry).
✅ Check 7 (no arch hacks): PASS — no --hf-overrides; fp8 KV-cache, block-size, batched-tokens are serving config, not model-FLOPs reduction.
➖ Check 8 (spec-decode chat template): N/A — no speculative-decoding changes.
✅ Check 9 (no engine patch): PASS — env-var exports and serve args only; pip install amd-quark is a stock upstream quantization dependency, not an engine fork/patch.
➖ Check 10 (agentic golden AL): N/A — no agentic speculative-decoding changes.

@Klaud-Cold

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❌❌❌ REJECTED ❌❌❌

@chunfangamd — blocking: this sign-off's Additional detail section links vllm-project/recipes#660, which documents the wrong model (amd/MiniMax-M3-MXFP4, models/MiniMaxAI/MiniMax-M3.yaml), not this PR's amd/Kimi-K2.5-MXFP4. The correct merged recipe #673 (models/moonshotai/Kimi-K2.5.yaml) is only linked in a later comment. Update this sign-off's Additional detail section to link #673, then re-run the gate.

✅ Check 0 (CODEOWNER): PASS — @chunfangamd owns configs/amd-master.yaml; the script + perf-changelog.yaml are catch-all (* @InferenceX/core), covered by any CODEOWNER.
✅ Check 1 (green in-PR sweep+eval): PASS — in-PR commit 45c6584 has executed, green single-node 8k1k / (TP4+TP8) and per-config eval / jobs in run 29953041481. (Head d1fd00e is a main-merge commit with all sweep jobs skipped; validation keys off any in-PR commit.)
✅ Check 2 (eval accuracy): PASS — GSM8K em_strict 96.89%–97.42% (n=1319) on amd/Kimi-K2.5-MXFP4, same image vllm/vllm-openai-rocm:nightly-387189c… as this PR's config.
❌ Check 3 (recipe merged+complete): FAIL — sign-off links #660 (MERGED, but documents amd/MiniMax-M3-MXFP4 with --tool-call-parser minimax_m3); model/model-path is a MAJOR arg and mismatches this PR's amd/Kimi-K2.5-MXFP4. The correct merged recipe #673 (Kimi-K2.5, merged 2026-07-23) is not linked in this sign-off — only in a separate comment. Link #673 in the Additional detail section.
✅ Check 4 (reuse command): PASS — /reuse-sweep-run posted by @chunfangamd (COLLABORATOR).
✅ Check 5 (latest template): PASS — all current-template items present; the two unchecked items (agentic spec-decode, catch-all reasoning) are non-applicable conditionals.
✅ Check 6 (upstream image / engine-first): PASS — vllm/vllm-openai-rocm:nightly-387189c… is the upstream vLLM org; framework: vllm, single-node established SKU MI355X. Engine-first N/A (vLLM entry).
✅ Check 7 (no arch hacks): PASS — no --hf-overrides; fp8 KV-cache / block-size / batched-tokens are serving config, not model-FLOPs reduction.
➖ Check 8 (spec-decode chat template): N/A — no speculative-decoding changes.
✅ Check 9 (no engine patch): PASS — env-var exports and serve args only; pip install amd-quark is a stock upstream quantization dependency, not an engine fork/patch.
➖ Check 10 (agentic golden AL): N/A — no agentic speculative-decoding changes.

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