[AMD] Tune Kimi-K2.5 MXFP4 MI355X vLLM toward ATOM parity / 调优 Kimi-K2.5 MXFP4 MI355X vLLM,缩小与 ATOM 的性能差距#2213
[AMD] Tune Kimi-K2.5 MXFP4 MI355X vLLM toward ATOM parity / 调优 Kimi-K2.5 MXFP4 MI355X vLLM,缩小与 ATOM 的性能差距#2213Fangzhou-Ai wants to merge 13 commits into
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Apply the accuracy-gated serving settings, preserve the existing TP4 and TP8 matrix dimensions, extend only their concurrency upper bounds to 128, and keep the image as a draft placeholder pending the required AITER bump. 中文:应用已通过精度验证的服务配置,保留现有 TP4 和 TP8 矩阵维度,仅将并发上限扩展到 128,并暂时保留镜像占位符,等待所需的 AITER 版本升级。
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… vLLM Replace image: TBD with rocm/vllm-dev:nightly_cdna4, the latest gfx950 serving image. It ships AITER 0.1.19.dev (>= v0.1.16.post5 from vllm-project/vllm#48683) including the ROCm/aiter#3832 gfx950 MXFP4 MoE backend required by this recipe. 中文:将 image: TBD 替换为最新的 gfx950 服务镜像 rocm/vllm-dev:nightly_cdna4。 该镜像内置 AITER 0.1.19.dev(不低于 vllm-project/vllm#48683 引入的 v0.1.16.post5), 包含本配方所需的 ROCm/aiter#3832 gfx950 MXFP4 MoE 后端。 Co-authored-by: Cursor <cursoragent@cursor.com>
…-tp4 Co-authored-by: Cursor <cursoragent@cursor.com> # Conflicts: # configs/amd-master.yaml # perf-changelog.yaml
…perf/kimi-k2.5-mi355x-tp4
…MI355X vLLM Use the reproducible dated build tag rocm/vllm-dev:nightly_cdna4_main_torch_2.11.0_rocm7.14.0a20260623_0721_b101 (same digest as floating nightly_cdna4) instead of the moving nightly_cdna4 tag. 中文:改用可复现的带日期构建标签 rocm/vllm-dev:nightly_cdna4_main_torch_2.11.0_rocm7.14.0a20260623_0721_b101 (与浮动的 nightly_cdna4 同一 digest),替换会被覆盖的 nightly_cdna4 标签。 Co-authored-by: Cursor <cursoragent@cursor.com>
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see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=29854639662 |
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see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=29855213440 |
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see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=29855213440 |
TP4/TP8 runs OOM during CUDA-graph capture: MI355X nodes hold ~30 GiB per GPU outside the vLLM process, so a 0.90 budget (259 GiB) leaves 0 bytes physically free and capture buffers cannot allocate. 0.85 keeps weights + KV inside 288 - 30 GiB with headroom for graph capture. 中文:将 MI355X 的 gpu-memory-utilization 从 0.90 下调到 0.85。TP4/TP8 在 CUDA graph 捕获阶段发生显存溢出——MI355X 节点每张卡有约 30 GiB 被 vLLM 进程之外占用,0.90 的预算(259 GiB)导致物理显存无剩余,捕获缓冲无法 分配。0.85 使权重与 KV 缓存控制在 288 - 30 GiB 内,为 graph 捕获留出余量。 Co-authored-by: Cursor <cursoragent@cursor.com>
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see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=29896096279 |
The AITER MXFP4 MoE bump (vllm-project/vllm#48683 / ROCm/aiter#3832) has landed in the floating rocm/vllm-dev:nightly_cdna4 tag, so drop the immutable dated pin and track nightly_cdna4 directly. 中文:改为跟踪浮动的 rocm/vllm-dev:nightly_cdna4 标签。AITER MXFP4 MoE 的版本提升(vllm-project/vllm#48683 / ROCm/aiter#3832)已合入 nightly_cdna4 浮动标签,因此去掉固定日期的镜像 pin,直接跟踪 nightly_cdna4。 Co-authored-by: Cursor <cursoragent@cursor.com>
…MI355X Switch the kimik2.5-fp4-mi355x-vllm image from the rocm/vllm-dev CDNA4 nightly to the official vllm/vllm-openai-rocm nightly, commit-pinned to the immutable nightly-387189c42997b27e2c04b5d97ef8190ffa2bf909 tag (latest as of 2026-07-22). It carries the AITER MXFP4 MoE bump (vllm-project/vllm#48683 / ROCm/aiter#3832) while staying reproducible. 中文:将 kimik2.5-fp4-mi355x-vllm 的镜像从 rocm/vllm-dev CDNA4 nightly 切换为官方 vllm/vllm-openai-rocm nightly,并按提交固定到不可变的 nightly-387189c42997b27e2c04b5d97ef8190ffa2bf909 标签(截至 2026-07-22 最新)。该镜像已包含 AITER MXFP4 MoE 的版本提升 (vllm-project/vllm#48683 / ROCm/aiter#3832),同时保持可复现。 Co-authored-by: Cursor <cursoragent@cursor.com>
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see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=29953041481 |
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As a PR reviewer and CODEOWNER, I have reviewed this and have:
- Verified that as of the moment of typing this, this is the latest version of PR_REVIEW_CHECKLIST.md
- Verified that the general code quality meets the InferenceX standard and does not make the code quality any worse.
- Verified that this PR has passed PR validation. Please link to GitHub Action workflow that shows this. Link: https://github.com/SemiAnalysisAI/InferenceX/actions/runs/29953041481
- Verified that this PR passes evals. Please link to GitHub Action workflow that shows this. Range: 96.89%-97.42%, link: https://github.com/SemiAnalysisAI/InferenceX/actions/runs/29953041481
- Verified that speculative decoding PRs uses chat templates to align the AL distribution to real world
- For agentic workloads: verified that speculative-decoding configs (EAGLE / MTP / draft models) run with simulated synthetic acceptance, with the acceptance-length value taken from the committed golden AL curve in golden_al_distribution/ for that model, thinking mode, and draft length. A submission may choose any supported draft length, but it may not substitute a different acceptance target.
- Verified that the model architecture isn't changed with benchmark hacks like using --hf-overrides to skipping indexer for every x layers on models that don't natively support this. As a general rule, we won't accept optimizations that reduces the number of model architecture FLOPs. Anything that makes that same computation run faster is fair game; FLOPs at lower precisions is fine, given that the config passes private evals. As an general north star princple, we should only use optimizations which is used in production by customers that care about accuracy
- If an company claims that they support vLLM/SGLang as first class LLM inference engines on their hardware, I have verified that the respective vLLM submission made using upstream https://hub.docker.com/u/vllm docker repo, upstream SGLang https://hub.docker.com/u/lmsysorg docker repo. The only exceptions are for new hardware, such as MI455X UALoE72, Vera Rubin NVL72, Rubin NVL8, etc., and for new model architectures where there is an actual reason why vLLM/SGLang does not fundamentally support them yet as supported by vLLM/SGLang community maintainers
- If an company claims that they support vLLM/SGLang as first class upstream in-tree LLM inference engines on their hardware, I have have verified that the respective vLLM/SGLang submission has been made before additional frameworks (TRT-LLM, ATOM, etc.). The only exceptions are for new hardware, such as MI455X UALoE72, Vera Rubin NVL72, Rubin NVL8, etc., and for new model architectures where there is an actual reason why vLLM/SGLang does not fundamentally support them yet.
- Verified that every single-node vLLM/SGLang recipe in this PR is documented in the official vLLM recipes and/or the SGLang cookbook:
- I linked the corresponding upstream PR in the vLLM recipe repo or SGLang repo and verified that it is MERGED before this InferenceX PR merges. An opened, draft, or closed-without-merge upstream PR does not satisfy this requirement. If the matching recipe was already published, I linked the published recipe/cookbook page in the additional detail section below.
- Verified that this PR does not patch the inference engine or serving stack — the pinned image must run as shipped. This covers .patch files / git apply / patch, inline patches embedded in benchmark scripts (e.g. a python3/sed heredoc that rewrites installed engine sources before serving), in-place edits of site-packages, monkey-patching, overwriting container files, and installing forked/rebuilt engine wheels on top of the pinned image. The only exception is a patch covered by a filled-out waiver at docs/waiver/
<PR_NUMBER>.md— named after the PR that introduces the patch and filed in that same PR, stating what is patched, why the unmodified upstream image cannot run this benchmark, the upstream PR/issue link, and the removal plan — which I have linked below in the additional detail section. - If any of the above criteria cannot reasonably be satisfied, I have provided additional reasoning below.
Additional detail section:
- insert any additional info here
vllm-project/recipes#660
Signed: @chunfangamd
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/reuse-sweep-run |
❌❌❌ REJECTED ❌❌❌@chunfangamd — blocking: the linked recipe documents a different model. This PR benchmarks ➖ Check 0 (CODEOWNER): PASS — |
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@claude check the recipe RP: vllm-project/recipes#673 |
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Claude finished @chunfangamd's task in 1m 19s —— View job Recipe PR check — vllm-project/recipes#673
✅ This resolves the Check 3 blockerRecipe #673 — "[ROCm] Document Kimi-K2.5 MXFP4 MI355X benchmark reproduction" — is MERGED (merged
This is the fix for the earlier Klaud-Cold rejection, which failed Check 3 solely because #660 documented Settings cross-check (recipe vs. this PR's config)The recipe's reproduction section matches this PR's effective settings:
One minor discrepancy (non-blocking)The merged recipe reproduction command shows Bottom line: #673 satisfies the merged-upstream-recipe requirement for |
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@claude I approve this PR because the reported issue has been resolved. Signed: @chunfangamd |
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Claude finished @chunfangamd's task in 1m 42s —— View job Approval acknowledged — one step still needed to flip the red checkThanks @chunfangamd. I've verified the resolution, and the underlying blocker is resolved — but the
What's resolved ✅
What still blocks the green check
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As a PR reviewer and CODEOWNER, I have reviewed this and have:
Additional detail section:
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✅✅✅ Verdict: PASS ✅✅✅Supersedes the earlier REJECTED verdict on this SHA: that gate ran before vllm-project/recipes#673 merged and against the stale #660 link. The current sign-off links #673 (now MERGED), which documents the correct model, so Check 3 now passes. Green run: 29953041481. ✅ Check 0 (CODEOWNER): PASS — |
❌❌❌ REJECTED ❌❌❌@chunfangamd — blocking: this sign-off's Additional detail section links vllm-project/recipes#660, which documents the wrong model ( ✅ Check 0 (CODEOWNER): PASS — |
Summary
amd/Kimi-K2.5-MXFP4on MI355X with vLLM TP4.image: TBDintentionally. This draft must not receive a sweep label until an official upstream vLLM ROCm image includes the required AITER MXFP4 backend.conc-endfrom 64 to 128 for both fixed-sequence workloads. Local evidence covers TP4 1k/1k at concurrency 4, 16, 32, and 128; TP8, the remaining points, and 8k/1k remain pending the official-image sweep.Effective settings
The recipe also preserves the existing 0.90 GPU-memory utilization, MEC firmware workaround, trusted remote code, and multimodal encoder TP mode. It enforces a minimum server context of 9472 tokens so the 1k/1k configuration matches the locally validated server.
Local validation
These results validate local vLLM
94c0ef300with AITERb2dd7703d, not the pending image:bash -n benchmarks/single_node/fixed_seq_len/kimik2.5_fp4_mi355x.sh{4,8}× concurrency{4,8,16,32,64,128}×{1k/1k,8k/1k}.AITER requirement
The tested kernel path requires:
e7731930/ #3753: transitional FlyDSL 0.2.1 bump.26d40611/ #3764: FlyDSL 0.2.2 compatibility and pin.b2dd7703d/ #3832: gfx950 RadeonFlow MXFP4 MoE backend and Kimi tuning.Pinning
b2dd7703dor a released descendant is sufficient because it already contains the first two commits. AITERv0.1.17-rc0contains FlyDSL 0.2.2 but predates #3832, so it cannot reproduce the tested GEMM1/GEMM2 path.Relationship to #2203
This is a materially different, measured alternative to #2203; only one should merge. #2203 copies K2.6-derived settings such as block size 1, 65,536 batched tokens, AITER RMSNorm, and custom MLA/compilation choices. This draft carries the locally validated Kimi-K2.5 settings that passed throughput scaling and full GSM8K evaluation.
Draft blockers
vllm-project/recipesdocumentation required by InferenceX policy.full-sweep-fail-fast, including evals, on the final image.AI assistance was used to prepare the benchmark configuration and PR text. The submitter must review and defend every changed line.
中文说明
amd/Kimi-K2.5-MXFP4vLLM TP4 基准测试应用已通过精度验证的候选配置。image: TBD。在上游正式发布包含所需 AITER MXFP4 后端的 vLLM ROCm 镜像之前,本草稿 PR 不应添加扫描标签。conc-end从 64 扩展到 128。本地数据覆盖 TP4 1k/1k 的并发点 4、16、32 和 128;TP8、其余并发点与 8k/1k 需要在正式镜像发布后通过 CI 扫描验证。“Effective settings”代码块列出了完整启动配置。该配置还保留现有的 0.90 GPU 显存利用率、MEC 固件规避措施、
trust-remote-code和多模态编码器 TP 模式,并将服务端最小上下文长度设为 9472,以对齐本地验证的 1k/1k 配置。本地验证
上表数据来自本地 vLLM
94c0ef300与 AITERb2dd7703d,不代表待发布镜像的结果:候选配置在并发 4、16、32、128 下达到 ATOM 吞吐量的 91.81%–94.69%。GSM8K 共完成 1319/1319 个请求,严格和宽松 exact match 均为 97.35%。Shell 语法检查通过;定向矩阵生成了 24 个配置,即 TP{4,8}× 并发{4,8,16,32,64,128}×{1k/1k,8k/1k}。AITER 依赖
所测内核路径需要 ROCm/aiter
e7731930(#3753,过渡到 FlyDSL 0.2.1)、26d40611(#3764,兼容并固定 FlyDSL 0.2.2)以及b2dd7703d(#3832,为 gfx950 增加 RadeonFlow MXFP4 MoE 后端和 Kimi 调优)。直接使用b2dd7703d或包含它的后续正式版本即可,因为该提交已经包含前两项。AITER
v0.1.17-rc0虽然包含 FlyDSL 0.2.2,但发布时间早于 #3832,因此无法复现本次验证所用的 GEMM1/GEMM2 路径。与 #2203 的关系
本 PR 是与 #2203 实质不同、具有实测依据的替代方案,两者最终只能合并一个。#2203 复用了 K2.6 配置,包括 block size 1、65,536 batched tokens、AITER RMSNorm 以及自定义 MLA/编译选项;本草稿采用已完成吞吐量扩展测试和完整 GSM8K 评估的 Kimi-K2.5 候选配置。
草稿阻塞项
vllm-project/recipes文档。full-sweep-fail-fast。本 PR 的基准配置和说明文本使用了 AI 辅助。提交者必须逐行审核,并能够完整解释和维护这些改动。